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HM5164165F Series HM5165165F Series
64M EDO DRAM (4-Mword x 16-bit) 8k refresh/4k refresh
ADE-203-1058B(Z) Rev. 2.0 Nov. 30, 1999 Description
The Hitachi HM5164165F Series, HM5165165F Series are 64M-bit dynamic RAMs organized as 4,194,304word x 16-bit. They have realized high performance and low power by employing CMOS process technology. HM5164165F Series, HM5165165F Series offer Extended Data Out (EDO) Page Mode as a high speed access mode. They have the package variations of standard 50-pin plastic SOJ and standerd 50-pin plastic TSOPII
Features
* Single 3.3 V supply: 3.3 V 0.3 V * Access time: 50 ns/60 ns (max) * Power dissipation Active: 432 mW/396 mW (max) (HM5164165F Series) : 504 mW/432 mW (max) (HM5165165F Series) Standby : 1.8 mW (max) (CMOS interface) : 1.1 mW (max) (L-version) * EDO page mode capability * Refresh cycles RAS-only refresh 8192 cycles /64 ms (HM5164165F, HM5164165FL) 4096 cycles /64 ms (HM5165165F, HM5165165FL) CBR/Hidden refresh 4096 cycles /64 ms (HM5164165F, HM5164165FL, HM5165165F, HM5165165FL)
HM5164165F Series, HM5165165F Series
* 4 variations of refresh RAS-only refresh CAS-before-RAS refresh Hidden refresh Self refresh (L-version) * 2CAS-byte control * Battery backup operation (L-version)
Ordering Information
Type No. HM5164165FJ-5 HM5164165FJ-6 HM5164165FLJ-5 HM5164165FLJ-6 HM5165165FJ-5 HM5165165FJ-6 HM5165165FLJ-5 HM5165165FLJ-6 HM5164165FTT-5 HM5164165FTT-6 HM5164165FLTT-5 HM5164165FLTT-6 HM5165165FTT-5 HM5165165FTT-6 HM5165165FLTT-5 HM5165165FLTT-6 Access time 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 50 ns 60 ns 400-mil 50-pin plastic TSOP II (TTP-50DB) Package 400-mil 50-pin plastic SOJ (CP-50DA)
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HM5164165F Series, HM5165165F Series
Pin Arrangement (HM5164165F Series)
50-pin SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 50-pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC A12 A11 A10 A9 A8 A7 A6 VSS
Pin Description
Pin name A0 to A12 Function Address input -- Row/Refresh address A0 to A12 -- Column address A0 to A8 Data input/output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection
I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
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HM5164165F Series, HM5165165F Series
Pin Arrangement (HM5165165F Series)
50-pin SOJ VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS VCC I/O0 I/O1 I/O2 I/O3 VCC I/O4 I/O5 I/O6 I/O7 NC VCC WE RAS NC NC NC NC A0 A1 A2 A3 A4 A5 VCC 50-pin TSOP 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 (Top view) VSS I/O15 I/O14 I/O13 I/O12 VSS I/O11 I/O10 I/O9 I/O8 NC VSS LCAS UCAS OE NC NC NC A11 A10 A9 A8 A7 A6 VSS
Pin Description
Pin name A0 to A11 Function Address input -- Row/Refresh address A0 to A11 -- Column address A0 to A9 Data input/output Row address strobe Column address strobe Write enable Output enable Power supply Ground No connection
I/O0 to I/O15 RAS UCAS, LCAS WE OE VCC VSS NC
4
HM5164165F Series, HM5165165F Series
Block Diagram (HM5164165F Series)
RAS UCAS LCAS WE OE
Timing and control
A0 A1 to A8 Row decoder * * * Column address buffers
Column decoder 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array
* * *
I/O buffers
I/O0 to I/O15
Row address buffers
A9 to A12
5
HM5164165F Series, HM5165165F Series
Block Diagram (HM5165165F Series)
RAS UCAS LCAS WE OE
Timing and control
A0 A1 to A9 Row decoder * * * Column address buffers
Column decoder 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array 4M array
* * *
I/O buffers
I/O0 to I/O15
Row address buffers
A10 A11
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HM5164165F Series, HM5165165F Series
Operation Table
RAS H L L L L L L L L L L L L L H to L H to L H to L L LCAS x L H L L H L L H L L H L H H L L L UCAS WE x H L L H L L H L L H L L H L H L L x H H H L* L* L* L* L* L*
2 2 2 2 2 2
OE x L L L x x x H H H L to H L to H L to H x x x x H
I/O 0 to I/O 7 High-Z Dout High-Z Dout Din x Din Din x Din Dout/Din High-Z Dout/Din High-Z High-Z High-Z High-Z High-Z
I/O 8 to I/O 15 Operation High-Z High-Z Dout Dout x Din Din x Din Din High-Z Dout/Din Dout/Din High-Z High-Z High-Z High-Z High-Z Read cycle (Output disabled) RAS-only refresh cycle CAS-before-RAS refresh cycle or Self refresh cycle (L-version) Read-modify-write cycle Delayed write cycle Early write cycle Standby Read cycle
H to L H to L H to L x H H H H
Notes: 1. H: VIH (inactive) L: VIL (active) x: VIH or VIL 2. t WCS 0 ns: Early write cycle t WCS < 0 ns: Delayed write cycle 3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by the earliest of UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However write operation and output High-Z control are done independently by each UCAS, LCAS. ex. if RAS = H to L, LCAS = L, UCAS = H, then CAS-before-RAS refresh cycle is selected.
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HM5164165F Series, HM5165165F Series
Absolute Maximum Ratings
Parameter Terminal voltage on any pin relative to V SS Power supply voltage relative to V SS Short circuit output current Power dissipation Storage temperature Symbol VT VCC Iout PT Tstg Value -0.5 to VCC + 0.5 ( 4.6 V (max)) -0.5 to +4.6 50 1.0 -55 to +125 Unit V V mA W C
DC Operating Conditions
Parameter Supply voltage Symbol VCC VSS Input high voltage Input low voltage Ambient temperature range VIH VIL Ta Min 3.0 0 2.0 -0.3 0 Typ 3.3 0 -- -- -- Max 3.6 0 VCC + 0.3 0.8 70 Unit V V V V C Notes 1, 2 2 1 1
Notes: 1. All voltage referred to VSS . 2. The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be on the same level.
8
HM5164165F Series, HM5165165F Series
DC Characteristics (HM5164165F Series)
HM5164165F -5 Parameter Operating current* * Standby current
1, 2
-6 Max 120 2 Min -- -- Max 110 2 Unit mA mA Test conditions t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = tHPC min CMOS interface Dout = High-Z CBR refresh: tRC = 15.6 s t RAS 0.3 s CMOS interface RAS, UCAS, LCAS 0.2 V Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC1 I CC2 -- --
--
0.5
--
0.5
mA
Standby current (L-version)
I CC2
--
300
--
300
A
RAS-only refresh current*2 Standby current*
1
I CC3 I CC5
-- --
120 5
-- --
110 5
mA mA
CAS-before-RAS refresh current EDO page mode current*1, * 3 Battery backup current*4 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
I CC6 I CC7 I CC10
-- -- --
120 120 1.2
-- -- --
110 110 1.2
mA mA mA
I CC11
--
500
--
500
A
I LI I LO VOH VOL
-5 -5 2.4 0
5 5 VCC 0.4
-5 -5 2.4 0
5 5 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC . 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
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HM5164165F Series, HM5165165F Series
DC Characteristics (HM5165165F Series)
HM5165165F -5 Parameter Operating current* * Standby current
1, 2
-6 Max 140 2 Min -- -- Max 120 2 Unit mA mA Test conditions t RC = min TTL interface RAS, UCAS, LCAS = VIH Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z CMOS interface RAS, UCAS, LCAS VCC - 0.2 V Dout = High-Z t RC = min RAS = VIH UCAS, LCAS = VIL Dout = enable t RC = min RAS = VIL , CAS cycle, t HPC = tHPC min CMOS interface Dout = High-Z CBR refresh: tRC = 15.6 s t RAS 0.3 s CMOS interface RAS, UCAS, LCAS 0.2 V Dout = High-Z 0 V Vin VCC + 0.3 V 0 V Vout VCC Dout = disable High Iout = -2 mA Low Iout = 2 mA
Symbol Min I CC1 I CC2 -- --
--
0.5
--
0.5
mA
Standby current (L-version)
I CC2
--
300
--
300
A
RAS-only refresh current*2 Standby current*
1
I CC3 I CC5
-- --
140 5
-- --
120 5
mA mA
CAS-before-RAS refresh current EDO page mode current*1, * 3 Battery backup current*4 (Standby with CBR refresh) (L-version) Self refresh mode current (L-version) Input leakage current Output leakage current Output high voltage Output low voltage
I CC6 I CC7 I CC10
-- -- --
140 120 1.2
-- -- --
120 110 1.2
mA mA mA
I CC11
--
500
--
500
A
I LI I LO VOH VOL
-5 -5 2.4 0
5 5 VCC 0.4
-5 -5 2.4 0
5 5 VCC 0.4
A A V V
Notes: 1. I CC depends on output load condition when the device is selected. ICC max is specified at the output open condition. 2. Address can be changed once or less while RAS = VIL. 3. Measured with one sequential address change per EDO cycle, tHPC . 4. VIH VCC - 0.2 V, 0 V VIL 0.2 V.
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HM5164165F Series, HM5165165F Series
Capacitance (Ta = 25C, VCC = 3.3 V 0.3 V)
Parameter Input capacitance (Address) Input capacitance (Clocks) Output capacitance (Data-in, Data-out) Symbol CI1 CI2 CI/O Min -- -- -- Typ -- -- -- Max 5 7 7 Unit pF pF pF Notes 1 1 1, 2
Notes : 1. Capacitance measured with Boonton Meter or effective capacitance measuring method. 2. RAS, UCAS and LCAS = VIH to disable Dout.
11
HM5164165F Series, HM5165165F Series
AC Characteristics (Ta = 0 to +70C, VCC = 3.3 V 0.3 V, VSS = 0 V)*1, *2, *19, *26
Test Conditions * * * * * Input rise and fall time: 2 ns Input pulse levels: V IL = 0 V, V IH = 3.0 V Input timing reference levels: 0.8 V, 2.0 V Output timing reference levels: 0.8 V, 2.0 V Output load: 1 TTL gate + C L (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common parameters)
HM5164165F/HM5165165F -5 Parameter Random read or write cycle time RAS precharge time CAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time OE to Din delay time OE delay time from Din CAS delay time from Din Transition time (rise and fall) Symbol t RC t RP t CP t RAS t CAS t ASR t RAH t ASC t CAH t RCD t RAD t RSH t CSH t CRP t OED t DZO t DZC tT Min 84 30 8 50 8 0 8 0 8 12 10 13 35 5 13 0 0 2 Max -- -- -- 10000 10000 -- -- -- -- 37 25 -- -- -- -- -- -- 50 -6 Min 104 40 10 60 10 0 10 0 10 14 12 15 40 5 15 0 0 2 Max -- -- -- 10000 10000 -- -- -- -- 45 30 -- -- -- -- -- -- 50 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 28 5 6 6 7 27 27 3 4 30 Notes
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HM5164165F Series, HM5165165F Series
Read Cycle
HM5164165F/HM5165165F -5 Parameter Access time from RAS Access time from CAS Access time from address Access time from OE Read command setup time Read command hold time to CAS Read command hold time from RAS Read command hold time to RAS Column address to RAS lead time Column address to CAS lead time CAS to output in low-Z Output data hold time Output data hold time from OE Output buffer turn-off time Output buffer turn-off to OE CAS to Din delay time Output data hold time from RAS Output buffer turn-off to RAS Output buffer turn-off to WE WE to Din delay time RAS to Din delay time Symbol t RAC t CAC t AA t OEA t RCS t RCH t RCHR t RRH t RAL t CAL t CLZ t OH t OHO t OFF t OEZ t CDD t OHR t OFR t WEZ t WED t RDD Min -- -- -- -- 0 0 50 0 25 15 0 3 3 -- -- 13 3 -- -- 13 13 Max 50 13 25 13 -- -- -- -- -- -- -- -- -- 13 13 -- -- 13 13 -- -- -6 Min -- -- -- -- 0 0 60 0 30 18 0 3 3 -- -- 15 3 -- -- 15 15 Max 60 15 30 15 -- -- -- -- -- -- -- -- -- 15 15 -- -- 15 15 -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 13, 21 13 5 21 13, 21 13 21 12 Notes 8, 9 9, 10, 17 9, 11, 17 9 27 12, 28
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HM5164165F Series, HM5165165F Series
Write Cycle
HM5164165F/HM5165165F -5 Parameter Write command setup time Write command hold time Write command pulse width Write command to RAS lead time Write command to CAS lead time Data-in setup time Data-in hold time Symbol t WCS t WCH t WP t RWL t CWL t DS t DH Min 0 8 8 13 8 0 8 Max -- -- -- -- -- -- -- -6 Min 0 10 10 15 10 0 10 Max -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns 29 15, 29 15, 29 Notes 14, 27 27
Read-Modify-Write Cycle
HM5164165F/HM5165165F -5 Parameter Read-modify-write cycle time RAS to WE delay time CAS to WE delay time Column address to WE delay time OE hold time from WE Symbol t RWC t RWD t CWD t AWD t OEH Min 116 67 30 42 13 Max -- -- -- -- -- -6 Min 140 79 34 49 15 Max -- -- -- -- -- Unit ns ns ns ns ns 14 14 14 Notes
Refresh Cycle
HM5164165F/HM5165165F -5 Parameter CAS setup time (CBR refresh cycle) CAS hold time (CBR refresh cycle) WE setup time (CBR refresh cycle) WE hold time (CBR refresh cycle) RAS precharge to CAS hold time Symbol t CSR t CHR t WRP t WRH t RPC Min 5 8 0 8 5 Max -- -- -- -- -- -6 Min 5 10 0 10 5 Max -- -- -- -- -- Unit ns ns ns ns ns 27 Notes 27 28
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HM5164165F Series, HM5165165F Series
EDO Page Mode Cycle
HM5164165F/HM5165165F -5 Parameter EDO page mode cycle time EDO page mode RAS pulse width Access time from CAS precharge RAS hold time from CAS precharge Output data hold time from CAS low CAS hold time referred OE CAS to OE setup time Read command hold time from CAS precharge OE precharge time Symbol t HPC t RASP t CPA t CPRH t DOH t COL t COP t RCHC Min 20 -- -- 28 3 8 5 28 8 8 Max -- -6 Min 25 Max -- Unit ns Notes 20 16 9, 17, 28
100000 -- 28 -- -- -- -- -- -- -- -- 35 3 10 5 35 10 10
100000 ns 35 -- -- -- -- -- -- -- ns ns ns ns ns ns ns ns
9, 22
Write pulse width during CAS precharge t WPE t OEP
EDO Page Mode Read-Modify-Write Cycle
HM5164165F/HM5165165F -5 Parameter Symbol Min 57 45 Max -- -- -6 Min 68 54 Max -- -- Unit ns ns 14, 28 Notes
EDO page mode read-modify-write cycle t HPRWC time WE delay time from CAS precharge t CPW
Refresh (HM5164165F Series)
Parameter Refresh period Symbol t REF Max 64 Unit ms Note 8192 cycles
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HM5164165F Series, HM5165165F Series
Refresh (HM5165165F Series)
Parameter Refresh period Symbol t REF Max 64 Unit ms Note 4096 cycles
Self Refresh Mode (L-version)
HM5164165FL/HM5165165FL -5 Parameter RAS pulse width (self refresh) RAS precharge time (self refresh) CAS hold time (self refresh) Symbol t RASS t RPS t CHS Min 100 90 -50 Max -- -- -- -6 Min 100 110 -50 Max -- -- -- Unit s ns ns Notes 25 25 29
Notes: 1. AC measurements assume t T = 2 ns. 2. An initial pause of 200 s is required after power up followed by a minimum of eight initialization cycles (any combination of cycles containing RAS-only refresh or CAS-before-RAS refresh). 3. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a reference point only; if t RCD is greater than the specified tRCD (max) limit, than the access time is controlled exclusively by tCAC . 4. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a reference point only; if t RAD is greater than the specified tRAD (max) limit, then access time is controlled exclusively by tAA . 5. Either t OED or tCDD must be satisfied. 6. Either t DZO or tDZC must be satisfied. 7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition times are measured between V IH (min) and VIL (max). 8. Assumes that t RCD tRCD (max) and tRAD tRAD (max). If tRCD or tRAD is greater than the maximum recommended value shown in this table, t RAC exceeds the value shown. 9. Measured with a load circuit equivalent to 1 TTL loads and 100 pF. 10. Assumes that t RCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max). 11. Assumes that t RAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max). 12. Either t RCH or tRRH must be satisfied for a read cycles. 13. t OFF (max), tOEZ (max), tWEZ (max) and tOFR (max) define the time at which the outputs achieve the open circuit condition and are not referred to output voltage levels. 14. t WCS , t RWD, t CWD, t AWD and t CPW are not restrictive operating parameters. They are included in the data sheet as electrical characteristics only; if t WCS tWCS (min), the cycle is an early write cycle and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if t RWD tRWD (min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW (min), the cycle is a read-modify-write and the data output will contain data read from the selected cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access time) is indeterminate. 15. t DS and t DH are referred to UCAS and LCAS leading edge in early write cycles and to WE leading edge in delayed write or read-modify-write cycles.
16
HM5164165F Series, HM5165165F Series
16. t RASP defines RAS pulse width in EDO page mode cycles. 17. Access time is determined by the longest among t AA , t CAC and t CPA. 18. In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to the device. 19. When output buffers are enabled once, sustain the low impedance state until valid data is obtained. When output buffer is turned on and off within a very short time, generally it causes large VCC/VSS line noise, which causes to degrade VIH min/VIL max level. 20. t HPC (min) can be achieved during a series of EDO page mode write cycles or EDO page mode read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle (EDO page mode mix cycle (1), (2)), minimum value of CAS cycle (tCAS + tCP + 2 tT) becomes greater than the specified t HPC (min) value.The value of CAS cycle time of mixed EDO page mode is shown in EDO page mode mix cycle (1) and (2). 21. Data output turns off and becomes high impedance from later rising edge of RAS and CAS. Hold time and turn off time are specified by the timing specifications of later rising edge of RAS and CAS between tOHR and t OH , and between t OFR and t OFF. 22. t DOH defines the time at which the output level go cross. V OL = 0.8 V, VOH = 2.0 V of output timing reference level. 23. Before and after self refresh mode, execute CBR refresh to all refresh addresses in or within 64 ms period on the condition a and b below. a. Enter self refresh mode within 15.6 s after either burst refresh or distributed refresh at equal interval to all refresh addresses are completed. b. Start burst refresh or distributed refresh at equal interval to all refresh addresses within 15.6s after exiting from self refresh mode. 24. In case of entering from RAS-only-refresh, it is necessary to execute CBR refresh before and after self refresh mode according as note 23. 25 At t RASS > 100 s, self refresh mode is activated, and not activated at tRASS < 10 s. It is undefined within the range of 10 s t RASS 100 s. For tRASS 10 s, it is necessary to satisfy tRPS. 26. When both UCAS and LCAS go low at the same time, all 16-bit data are written into the device. UCAS and LCAS cannot be staggered within the same write/read cycles. 27. t ASC, tCAH , t RCS , t WCS , t WCH, t CSR and t RPC are determined by the earlier falling edge of UCAS or LCAS. 28. t CRP , t CHR, t RCH, t CPA and tCPW are determined by the later rising edge of UCAS or LCAS. 29. t CWL, t DH, t DS and t CHS should be satisfied by both UCAS and LCAS. 30. t CP is determined by the time that both UCAS and LCAS are high. 31. XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max)) ///////: Invalid Dout When the address, clock and input pins are not described on timing waveforms, their pins must be applied V IH or VIL.
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HM5164165F Series, HM5165165F Series
Notes concerning 2CAS control
Please do not separate the UCAS/LCAS operation timing intentionally. UCAS/LCAS are allowed under the following conditions. However skew between
1. Each of the UCAS/LCAS should satisfy the timing specifications individually. 2. Different operation mode for upper/lower byte is not allowed; such as following.
RAS Delayed write UCAS Early write LCAS
WE
3. Closely separated upper/lower byte control is not allowed. However when the condition (tCP tUL) is satisfied, EDO page mode can be performed.
RAS
UCAS
LCAS t UL
4. Byte control operation by remaining UCAS or LCAS high is guaranteed.
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HM5164165F Series, HM5165165F Series
Timing Waveforms*31
Read Cycle
tRC tRAS RAS tCSH tT tRCD tRSH tCAS tCRP
tRP
UCAS LCAS tASR
tRAD tRAH tASC
tRAL tCAL tCAH
Address
Row
Column tRRH tRCHR tRCS tRCH
WE tDZC tWED
tCDD tRDD
Din
High-Z
tDZO
tOEA
tOED
OE tCAC tAA tRAC tCLZ tOEZ tOHO tOFF tOH tOFR tOHR tWEZ Dout Dout
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HM5164165F Series, HM5165165F Series
Early Write Cycle
tRC tRAS tRP
RAS tCSH tRCD tT UCAS LCAS tRSH tCAS tCRP
tASR
tRAH
tASC
tCAH
Address
Row
Column
tWCS
tWCH
WE
tDS
tDH
Din
Din
Dout
High-Z*
* t WCS
t WCS (min)
20
HM5164165F Series, HM5165165F Series
Delayed Write Cycle*18
tRC tRAS
tRP
RAS tCSH tRCD tT UCAS LCAS tASR tRAH tASC tCAH tRSH tCAS tCRP
Address
Row
Column tCWL tRCS tRWL tWP
WE
tDZC
tDS
tDH
Din
High-Z
Din tOED
,
tDZO tOEH tOEP OE tOEZ tCLZ Dout High-Z Invalid Dout 21
HM5164165F Series, HM5165165F Series
Read-Modify-Write Cycle*18
tRWC tRAS
tRP
RAS tT tRCD tCAS tCRP
UCAS LCAS tASR
tRAD tRAH tASC tCAH
Address
Row tRCS
Column tCWD tAWD tRWD tCWL tRWL tWP
WE tDZC tDH
tDS High-Z
Din
Din tOED tOEH
,
tDZO tOEA tOEP OE tCAC tAA tOEZ tRAC tOHO Dout Dout High-Z tCLZ 22
HM5164165F Series, HM5165165F Series
RAS-Only Refresh Cycle
tRC tRAS
RAS
tRP
tT tCRP UCAS LCAS tASR
Address
tRPC
tCRP
tRAH
Row tOFR tOFF
Dout
High-Z
23
HM5164165F Series, HM5165165F Series
CAS-Before-RAS Refresh Cycle
tRC tRP tRAS tRP tRAS tRC tRP
RAS tT tRPC tCP UCAS LCAS tWRP tWRH tWRP tWRH tCSR tCHR tRPC tCP tCSR tCHR tCRP
WE
Address tOFR tOFF Dout High-Z
24
HM5164165F Series, HM5165165F Series
Hidden Refresh Cycle
tRC tRAS tRP tRC tRAS tRP tRAS tRC tRP
RAS
tT tRSH tRCD tCHR tCRP
UCAS LCAS
tRAD tASR tRAH tASC tRAL tCAH
Address
Row
Column
tRRH tRCS tRCH
WE
tDZC tWED tCDD tRDD
High-Z Din
tDZO tOEA
tOED
OE
tCAC tAA tRAC tCLZ tOFF tOH tOEZ tWEZ tOHO
Dout
Dout
tOFR tOHR
25
HM5164165F Series, HM5165165F Series
EDO Page Mode Read Cycle
t RP
RAS
t RASP tT t CSH t CAS t RCS t RCHR t RCH t RCS t CP t HPC t CAS t CP t HPC tCAS t RCHC
t HPC t CPRH t CP t t CRP
RSH
UCAS LCAS
tCAS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t WPE t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL tDZC
t CAL tRDD tCDD
Din
High-Z tDZO tCOL tOEP tCOP tOEP tOED

OE
tOEA
tCPA
tCPA
tCAC tAA
tAA tCAC
tOEZ
tWEZ
tOHO
tCPA tAA tCAC
tAA
tOEZ
tOFR tOHR tOEZ tOHO tOFF tOH
tCAC
tRAC
tOEA
tDOH
tOHO
tOEA
Dout
Dout 1
Dout 2
Dout 2
Dout 3
Dout 4
26
HM5164165F Series, HM5165165F Series
EDO Page Mode Read Cycle (2CAS control)
t RP
RAS
t RASP t HPC t CAS tHPC
t CP
tT
LCAS
t CSH t CAS
t CP
t CP
t HPC tRSH tCAS
t CRP
UCAS
t CAS t RCHC t RCS t RRH t RCH
WE
tASR
Address
tRAH tASC Row
tCAH
t ASC t CAH Column 2 t CAL
t ASC t CAH Column 3 t CAL
tASC
t RAL t CAH
Column 4
t WED
Column 1 t CAL
tDZC
t CAL
tRDD tCDD
Din
High-Z tDZO tOEP tCOL tOEP tCOP tOED
OE
tOEA tCAC tAA
tCPA tAA tCAC tDOH tOEZ tOHO tOEZ tOEA
tCPA tAA tCAC
tOFR tOHR tOEZ tOHO tOFF tOH
tRAC tOHO
L Dout
Dout 1
Dout 2
Dout 2
Dout 4
tCPA tAA tCAC
tOEA
U Dout
Dout 1
Dout 3
Dout 4
27
HM5164165F Series, HM5165165F Series
EDO Page Mode Early Write Cycle
tRASP tRP
RAS tT tRCD UCAS LCAS
tCSH tCAS tCP
tHPC tCAS tCP
tRSH tCAS tCRP
tASR
tRAH
tASC
tCAH
tASC
tCAH
tASC
tCAH
Address
Row
Column 1
Column 2
Column N
tWCS
tWCH
tWCS
tWCH
tWCS
tWCH
WE
tDS
tDH
tDS
tDH
tDS
tDH
Din
Din 1
Din 2
Din N
Dout
High-Z*
* t WCS
t WCS (min)
28
HM5164165F Series, HM5165165F Series
EDO Page Mode Delayed Write Cycle*18
tRASP tRP RAS tT tCSH tRCD UCAS LCAS tRAD tASR tRAH Address Row tASC tCAH Column 1 tCWL tRCS WE tWP tDZC tDS tDH Din tDZO tOED tOEP tOEH OE Din 1 tDZO tDZC tWP tDS tDH Din 2 tOED tOEP tOEH tDZO tDZC tWP tDS tDH Din N tOED tOEP tOEH tRCS tASC tCAH Column 2 tCWL tRCS tASC tCAH Column N tCWL tRWL tCAS tCP tHPC tCAS tCP tRSH tCAS tCRP

tCLZ tCLZ tCLZ tOEZ tOEZ Dout Invalid Dout Invalid Dout Invalid Dout
tOEZ High-Z
29
HM5164165F Series, HM5165165F Series
EDO Page Mode Read-Modify-Write Cycle*18
t RASP t RP RAS tT t CP t RCD
UCAS LCAS
t HPRWC t CP t CAS t CAS
t RSH t CAS
t CRP
t RAD t ASR t ASC t RAH Row t CAH Column 1 t RWD t AWD t CWD WE t RCS t WP t DZC t DS t DH Din t DZO t OED t OEP t OEH Din 1 t DZO t OED t OEP t OEH t WP t DZC t DS t DH Din 2 t DZO t OED t OEP t OEH t WP t DZC t DS t DH Din N t CWL t RCS t ASC t CAH Column 2 t CPW t AWD t CWD t RCS t CWL t ASC t CAH Column N t CPW t AWD t CWD t RWL t CWL
Address
*
OE t OHO t OHO t OHO t AA t OEA t CAC t RAC t AA t CPA t OEA t CAC t AA t CPA t OEA t CAC t CLZ t OEZ t CLZ t OEZ t CLZ t OEZ
High-Z
Dout
Dout 1
Dout 2
Dout N
30
HM5164165F Series, HM5165165F Series
EDO Page Mode Mix Cycle (1) *20
t RP
RAS
t RASP t CRP tCAS tCWL t RCS tCPW tAWD t ASC tRAH Row tCAH t ASC t CAH Column 2 t CAL t DS t DH Din 1 High-Z tOED t DS t DH Din 3 tOEP tWED tASC t CAH Column 3 tWP t RAL t CAH Column 4 t CAL tRDD tCDD t RCS tRSH t RRH t RCH
tT
UCAS LCAS
t CP t CAS t CSH t RCD t WCS t WCH t CAS
t CP tCAS
t CP
WE
tASR
Address
tASC
Column 1
Din

OE
tCPA tAA tOEA
tCPA
tCPA tAA
t OEZ
tAA
tOFR tWEZ tOEZ
tCAC
tOHO tOFF tOH
tCAC
t DOH
tCAC t OHO
tOEA
Dout
Dout 2
Dout 3
Dout 4
31
HM5164165F Series, HM5165165F Series
EDO Page Mode Mix Cycle (2)*20
t RP
RAS
t RASP CAS tT
t CSH t CAS t RCD t RCS t RCHR
t CP t CAS
t CP tCAS tCWL t RCS tCPW
t CP tCAS t RCS tWP t RAL tASC t CAH Column 4 t CAL t DS tRSH
t CRP
UCAS LCAS
t RCH tWCS t WCH
t RRH t RCH
WE
tASR
Address
tRAH Row
t ASC
tCAH
t ASC t CAH Column 2
t ASC t CAH Column 3
Column 1 t CAL
t DS
Din
t DH Din 2
t DH Din 3 t OEP tOED tCOL tCOP
tRDD tCDD
High-Z
t OEP tOED
OE
tWED
tAA tOEA tCAC tRAC t OHO
Dout
t OEA tOEZ tCPA tAA tCAC tOEZ t OHO
Dout 3
tCPA tAA tCAC tOEA
tOFR tWEZ tOEZ tOHO tOFF tOH Dout 4
Dout 1
32
HM5164165F Series, HM5165165F Series
Self Refresh Cycle (L-version)* 23, 24, 25
tRASS
tRP
tRPS
RAS tRPC tT
, ,
tCP tCSR UCAS LCAS tWRP WE tOFR tOFF Dout
tCRP tCHS
tWRH
, + & $
High-Z 33
HM5164165F Series, HM5165165F Series
Package Dimensions
HM5164165FJ/FLJ Series HM5165165FJ/FLJ Series (CP-50DA)
Unit: mm
20.95 21.38 Max
50
26 10.16 0.13 11.18 0.13
1
0.47
25 3.50 0.26 0.90 0.26 2.55 0.12 9.40 0.25
CP-50DA Conforms -- 1.2 g
1.09 Max
*0.32 0.08 0.30 0.04
0.80 0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
34
HM5164165F Series, HM5165165F Series
HM5164165FTT/FLTT Series HM5165165FTT/FLTT Series (TTP-50DB)
Unit: mm
20.95 21.35 Max 50 26
1
0.10 *0.30 + 0.05 - 0.28 0.05
0.80 0.13 M
25
10.16
0.80 11.76 0.20 0 - 5 *0.145 0.05 0.125 0.04 0.13 0.05 0.68 0.50 0.10
1.15 Max
1.20 Max
0.10
*Dimension including the plating thickness Base material dimension
Hitachi Code JEDEC EIAJ Weight (reference value)
TTP-50DB -- -- 0.51 g
35
HM5164165F Series, HM5165165F Series
Cautions
1. Hitachi neither warrants nor grants licenses of any rights of Hitachi's or any third party's patent, copyright, trademark, or other intellectual property rights for information contained in this document. Hitachi bears no responsibility for problems that may arise with third party's rights, including intellectual property rights, in connection with use of the information contained in this document. 2. Products and product specifications may be subject to change without notice. Confirm that you have received the latest product standards or specifications before final design, purchase or use. 3. Hitachi makes every attempt to ensure that its products are of high quality and reliability. However, contact Hitachi's sales office before using the product in an application that demands especially high quality and reliability or where its failure or malfunction may directly threaten human life or cause risk of bodily injury, such as aerospace, aeronautics, nuclear power, combustion control, transportation, traffic, safety equipment or medical equipment for life support. 4. Design your application so that the product is used within the ranges guaranteed by Hitachi particularly for maximum rating, operating supply voltage range, heat radiation characteristics, installation conditions and other characteristics. Hitachi bears no responsibility for failure or damage when used beyond the guaranteed ranges. Even within the guaranteed ranges, consider normally foreseeable failure rates or failure modes in semiconductor devices and employ systemic measures such as fail-safes, so that the equipment incorporating Hitachi product does not cause bodily injury, fire or other consequential damage due to operation of the Hitachi product. 5. This product is not designed to be radiation resistant. 6. No one is permitted to reproduce or duplicate, in any form, the whole or part of this document without written approval from Hitachi. 7. Contact Hitachi's sales office for any questions regarding this document or Hitachi semiconductor products.
Hitachi, Ltd.
Semiconductor & Integrated Circuits. Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100-0004, Japan Tel: Tokyo (03) 3270-2111 Fax: (03) 3270-5109
URL
NorthAmerica : http:semiconductor.hitachi.com/ Europe : http://www.hitachi-eu.com/hel/ecg Asia (Singapore) : http://www.has.hitachi.com.sg/grp3/sicd/index.htm Asia (Taiwan) : http://www.hitachi.com.tw/E/Product/SICD_Frame.htm Asia (HongKong) : http://www.hitachi.com.hk/eng/bo/grp3/index.htm Japan : http://www.hitachi.co.jp/Sicd/indx.htm For further information write to:
Hitachi Europe GmbH Electronic components Group Dornacher Strae 3 D-85622 Feldkirchen, Munich Germany Tel: <49> (89) 9 9180-0 Fax: <49> (89) 9 29 30 00 Hitachi Europe Ltd. Electronic Components Group. Whitebrook Park Lower Cookham Road Maidenhead Berkshire SL6 8YA, United Kingdom Tel: <44> (1628) 585000 Fax: <44> (1628) 778322 Hitachi Asia Pte. Ltd. 16 Collyer Quay #20-00 Hitachi Tower Singapore 049318 Tel: 535-2100 Fax: 535-1533 Hitachi Asia Ltd. Taipei Branch Office 3F, Hung Kuo Building. No.167, Tun-Hwa North Road, Taipei (105) Tel: <886> (2) 2718-3666 Fax: <886> (2) 2718-8180 Hitachi Asia (Hong Kong) Ltd. Group III (Electronic Components) 7/F., North Tower, World Finance Centre, Harbour City, Canton Road, Tsim Sha Tsui, Kowloon, Hong Kong Tel: <852> (2) 735 9218 Fax: <852> (2) 730 0281 Telex: 40815 HITEC HX
Hitachi Semiconductor (America) Inc. 179 East Tasman Drive, San Jose,CA 95134 Tel: <1> (408) 433-1990 Fax: <1>(408) 433-0223
Copyright (c) Hitachi, Ltd., 1998. All rights reserved. Printed in Japan.
36
HM5164165F Series, HM5165165F Series
Revision Record
Rev. Date 0.0 1.0 Contents of Modification Drawn by M. Kawamura M. Kawamura Approved by M. Mishima Y. Kasama May. 25, 1999 Initial issue Oct. 5, 1999 Features: Change of Power dissipation Standby (L-version) max: TBD to 1.1 mW DC Characteristics I CC2 (L-version) max: TBD/TBD to 300/300 A I CC10 (L-version) max: TBD/TBD to 1/1 mA I CC11 (L-version) max: TBD/TBD to 500/500 A DC Characteristics I CC10 (L-version) max: 1/1 mA to 1.2/1.2 mA
2.0
Nov. 30, 1999
37

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